Table Of Contents
Table Of Contents

code_generator.py

class fabric_generator.code_generator.codeGenerator

The base class for all code generators.

abstract addAssignScalar(left, right, delay=0, indentLevel=0)

Add a scalar assign statement. Delay is provided by currently not being used by any of the code generator. If right is a list, it will be concatenated. Verilog will be concatenated with comma ‘,’. VHDL will be concatenated with ampersand ‘&’.

Examples :
Verilog: assign left = right;
VHDL: left <= right after delay ps;
Parameters

  • left – The left hand side of the assign statement.

  • right – The right hand side of the assign statement.

  • delay (int, optional) – delay in the assignment. Defaults to 0.

  • indentLevel (int, optional) – The indentation Level. Defaults to 0.

abstract addAssignVector(left, right, widthL, widthR, indentLevel=0)

Add a vector assign statement.

Examples :
Verilog: assign left = right [widthL:widthR];
VHDL: left <= right ( widthL downto widthR );
Parameters

  • left – The left hand side of the assign statement.

  • right – The right hand side of the assign statement.

  • widthL – The start index of the vector. Can be a string.

  • widthR – The end index of the vector. Can be a string.

  • indentLevel (int, optional) – The indentation Level. Defaults to 0.

abstract addComment(comment: str, onNewLine=False, end='', indentLevel=0) → None

Add a comment to the code.

Examples :
Verilog: // comment
VHDL : – comment
Parameters

  • comment (str) – The comment

  • onNewLine (bool, optional) – If true put the comment on a new line. Defaults to False.

  • end (str, optional) – The end token of the comment. Defaults to “”.

  • indentLevel (int, optional) – The indentation Level. Defaults to 0.

abstract addComponentDeclarationForFile(fileName: str)

Add a component declaration for a file. Only useful with VHDL. Will copy the entity of the file, and replacing the entity with component for VHDL to work.

Parameters

fileName (str) – name of the VHDL file

abstract addConnectionScalar(name: str, indentLevel=0)

Add a scalar connection.

Examples :
Verilog: wire name;
VHDL: signal name : STD_LOGIC;
Parameters

  • name (str) – name of the connection

  • indentLevel (int, optional) – The indentation Level. Defaults to 0.

abstract addConnectionVector(name: str, startIndex, endIndex=0, indentLevel=0)

Add a vector connection.

Examples :
Verilog: wire [startIndex:end] name;
VHDL: signal name : STD_LOGIC_VECTOR( startIndex downto endIndex );
Parameters

  • name (str) – name of the connection

  • startIndex – Start index of the vector. Can be a string.

  • endIndex (int, optional) – End index of the vector. Can be a string. Defaults to 0.

  • indentLevel (int, optional) – The indentation Level. Defaults to 0.

abstract addConstant(name: str, value, indentLevel=0)

Add a constant.

Examples :
Verilog: parameter name = value;
VHDL: constant name : STD_LOGIC := value;
Parameters

  • name (str) – name of the constant

  • value – The value of the constant.

  • indentLevel (int, optional) – The indentation Level. Defaults to 0.

abstract addDesignDescriptionEnd(indentLevel=0)

Add end of design description.

Examples :
Verilog: endmodule
VHDL: end architecture Behavioral
Parameters

indentLevel (int, optional) – The indentation Level. Defaults to 0.

abstract addDesignDescriptionStart(name: str, indentLevel=0)

Add start of design description. Only useful with VHDL.

Examples :
Verilog:
VHDL: architecture Behavioral of name is
Parameters

  • name (str) – name of the module

  • indentLevel (int, optional) – The indentation Level. Defaults to 0.

abstract addFlipFlopChain(configBits: int, indentLevel=0)

Add a flip flop chain.

Parameters

  • configBits (int) – the number of config bits

  • indentLevel (int, optional) – The indentation Level. Defaults to 0.

abstract addHeader(name: str, package='', indentLevel=0)

Add a header to the code.

Examples :
Verilog: module name
VHDL: library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.ALL
package
entity name is
Parameters

  • name (str) – name of the module

  • package (str, optional) – The package used by VHDL. Only useful with VHDL. Defaults to ‘’.

  • indentLevel (int, optional) – The indentation Level. Defaults to 0.

abstract addHeaderEnd(name: str, indentLevel=0)

Add end to header. Only useful with VHDL.

Examples :
Verilog:
VHDL: end entity name;
Parameters

  • name (str) – name of the module

  • indentLevel (int, optional) – The indentation Level. Defaults to 0.

abstract addInstantiation(compName: str, compInsName: str, portsPairs: List[Tuple[str, str]], paramPairs: List[Tuple[str, str]] = [], emulateParamPairs: List[Tuple[str, str]] = [], indentLevel=0)

Add an instantiation. This will line up the ports and signals. So ports[0] will have signals[0] and so on. This is also the same case for paramPorts and paramSignals.

Examples :
Verilog: compName compInsName # (
. paramPorts[0] (paramSignals[0]),
. paramPorts[1] (paramSignals[1]),
…
. paramPorts[n] (paramSignals[n])
) (
. compPorts[0] (signals[0]),
. compPorts[1] (signals[1]),
…
. compPorts[n] (signals[n])
);
VHDL: compInsName : compName
generic map (
paramPorts[0] => paramSignals[0],
paramPorts[1] => paramSignals[1],
…
paramPorts[i] => paramSignals[i]
);
Port map (
compPorts[i] => signals[i],
compPorts[i] => signals[i],
compPorts[i] => signals[i]
);
Parameters

  • compName (str) – name of the component

  • compInsName (str) – name of the component instance

  • compPorts (List[str]) – list of ports of the component

  • signals (List[str]) – list of signals of the component

  • paramPorts (List[str], optional) – list of parameter ports of the component. Defaults to [].

  • paramSignals (List[str], optional) – list of parameter signals of the component. Defaults to [].

  • emulateParamPairs (List[str], optional) – list of parameter signals of the component in emulation mode only. Defaults to [].

  • indentLevel (int, optional) – The indentation Level. Defaults to 0.

Raises

  • ValueError – If the number of compPorts and signals are not equal.

  • ValueError – If the number of paramPorts and paramSignals are not equal.

abstract addLogicEnd(indentLevel=0)

Add end of logic. Only useful with VHDL.

Examples :
Verilog:
VHDL: end
Parameters

indentLevel (int, optional) – The indentation Level. Defaults to 0.

abstract addLogicStart(indentLevel=0)

Add start of logic. Only useful with VHDL.

Examples :
Verilog:
VHDL: begin
Parameters

indentLevel (int, optional) – The indentation Level. Defaults to 0.

abstract addParameter(name: str, type, value, indentLevel=0)

Add a parameter.

Examples :
Verilog: parameter name = value
VHDL: name : type := value;
Parameters

  • name (str) – name of the parameter

  • type (_type_) – type of the parameter. Only useful with VHDL.

  • value (_type_) – value of the parameter.

  • indentLevel (int, optional) – The indentation Level. Defaults to 0.

abstract addParameterEnd(indentLevel=0)

Add end of parameters.

Examples :
Verilog: )
VHDL: );
Parameters

indentLevel (int, optional) – The indentation Level. Defaults to 0.

abstract addParameterStart(indentLevel=0)

Add start of parameters.

Examples :
Verilog: #(
VHDL: Generic(
Parameters

indentLevel (int, optional) – The indentation Level. Defaults to 0.

abstract addPortEnd(indentLevel=0)

Add end of ports.

Examples :
Verilog: );
VHDL: );
Parameters

indentLevel (int, optional) – The indentation Level. Defaults to 0.

abstract addPortScalar(name: str, io: fabric_generator.fabric.IO, indentLevel=0)

Add a scalar port.

Examples :
Verilog: io name
VHDL: name : io STD_LOGIC;
Parameters

  • name (str) – name of the port

  • io (IO) – direction of the port (input, output, inout)

  • indentLevel (int, optional) – The indentation Level. Defaults to 0.

abstract addPortStart(indentLevel=0)

Add start of ports.

Examples :
Verilog: (
VHDL: port (
Parameters

indentLevel (int, optional) – The indentation Level. Defaults to 0.

abstract addPortVector(name: str, io: fabric_generator.fabric.IO, msbIndex, indentLevel=0)

Add a vector port.

Examples :
Verilog: io [msbIndex:0] name
VHDL: name : io STD_LOGIC_VECTOR( msbIndex downto 0 );
Parameters

  • name (str) – name of the port

  • io (IO) – direction of the port (input, output, inout)

  • msbIndex (int) – index of the MSB of the vector. Can be a string

  • indentLevel (int, optional) – The indentation Level. Defaults to 0.

abstract addPreprocElse(indentLevel=0)

Add a preprocessor “else”

Examples :
Verilog: `else
VHDL: unsupported
Parameters

  • macro – The macro to check for

  • indentLevel (int, optional) – The indentation Level. Defaults to 0.

abstract addPreprocEndif(indentLevel=0)

Add a preprocessor “endif”

Examples :
Verilog: `endif
VHDL: unsupported
Parameters

  • macro – The macro to check for

  • indentLevel (int, optional) – The indentation Level. Defaults to 0.

abstract addPreprocIfDef(macro, indentLevel=0)

Add a preprocessor “ifdef”

Examples :
Verilog: `ifdef macro
VHDL: unsupported
Parameters

  • macro – The macro to check for

  • indentLevel (int, optional) – The indentation Level. Defaults to 0.

abstract addPreprocIfNotDef(macro, indentLevel=0)

Add a preprocessor “ifndef”

Examples :
Verilog: `ifndef macro
VHDL: unsupported
Parameters

  • macro – The macro to check for

  • indentLevel (int, optional) – The indentation Level. Defaults to 0.

abstract addShiftRegister(configBits: int, indentLevel=0)

Add a shift registers.

Parameters

  • configBits (int) – the number of config bits

  • indentLevel (int, optional) – The indentation Level. Defaults to 0.

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