Table Of Contents

FABulous: an Embedded FPGA Framework

FABulous is designed to fulfill the objectives of ease of use, maximum portability to different process nodes, good control for customization, and delivering good area, power, and performance characteristics of the generated FPGA fabrics. The framework provides templates for logic, arithmetic, memory, and I/O blocks that can be easily stitched together, whilst enabling users to add their own fully customized blocks and primitives.

The FABulous ecosystem generates the embedded FPGA fabric for chip fabrication, integrates SymbiFlow toolchain release packages, deals with the bitstream generation and after fabrication tests. Additionally, we will provide an emulation path for system development.

This guide describes everything you need to set up your system to develop for FABulous ecosystem.

FABulous workflows and dependencies.

Check out the Quick start section for further information, including Prerequisites.

Note

This project is under active development.

Contents

• Quick start
  • Prerequisites
  • Building Fabric and Bitstream
  • Running in a Docker container
• Building fabric
• Fabric definition
  • Fabric CSV description
  • Fabric layout
  • Tiles
  • Supertiles
• FPGA CAD-tool parameterization
  • Yosys models
  • Nextpnr models
  • VPR models
• RTL to Bitstream
  • Yosys compilation
  • Nextpnr compilation
  • VPR compilation
  • Bitstream generation
• Simulation and emulation
  • Simulation setup
  • Emulation setup
• Chip Gallery
• References
  • code_generator.py
  • fabric.py
  • fabric_gen.py
  • file_parser.py
  • model_generation_npnr.py
  • model_generation_vpr.py
• Definitions and abbreviations
• Team and Contact
• Publications

Table Of Contents

• FABulous: an Embedded FPGA Framework
  • Contents

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