cmd_user_design

User design flow commands for the FABulous REPL.

Synthesis, place-and-route, bitstream generation, simulation, and user design wrapper generation.

Classes

UserDesignCommandSet

User design flow: synthesis through bitstream and simulation.

Functions

collect_gl_sources(project, sim_lib_overrides)	Resolve every Verilog source the gate-level simulator needs.
resolve_sim_libs(project, overrides)	Resolve the PDK standard-cell Verilog sim models for project.

Module Contents

UserDesignCommandSet

class UserDesignCommandSet

Bases: ReplCommandSet

User design flow: synthesis through bitstream and simulation.

Private reference to the CLI instance in which this CommandSet running.

This will be set when the CommandSet is registered and it should be accessed by child classes using the self._cmd property.

Methods

do_compile_design(files, top='top_wrapper', json=None, synth_only=False, pnr_only=False, bitgen_only=False, synth_extra_args='', yosys_extra_args='', nextpnr_extra_args='', log=None, fasm=None, bin_file=None, yosys_synth_help=False, nextpnr_help=False) → None

Compile a user design through synthesis, PnR, and bitstream generation.

This function orchestrates the full compile flow by delegating to a compile Taskfile. It resolves input file paths, builds the synthesis command, and invokes the appropriate task(s) depending on the selected mode (full compile, synth-only, pnr-only, or no-bitgen).

do_gen_bitStream_binary(file) → None

Generate bitstream of a given design.

deprecated: Use compile_design which includes bitstream generation.

do_gen_user_design_wrapper(user_design, user_design_top_wrapper) → None

Generate a wrapper that connects the user design to the fabric.

do_place_and_route(file) → None

Run place and route with Nextpnr for a given JSON file.

deprecated: Use compile_design --pnr-only instead.

do_run_FABulous_bitstream(file) → None

Run FABulous to generate bitstream on a given design.

deprecated: Use compile_design instead.

do_run_simulation(output_format, file, design='', simulator='', extra_iverilog_flag='', extra_nvc_flag='', extra_ghdl_flag='', gl=False, gl_sim_libs=None) → None

Simulate given FPGA design.

Uses Taskfile.yml (preferred) or falls back to Make (deprecated). The bitstream_file argument should be a binary file generated by ‘compile_design’. With --gl the hardened fabric netlist replaces the behavioural core for gate-level simulation.

do_synthesis(files, top='top_wrapper', auto_top=False, blif=None, edif=None, json_file=None, lut='4', plib=None, extra_plib=None, extra_map=None, encfile=None, nofsm=False, noalumacc=False, carry='none', noregfile=False, iopad=False, complex_dff=False, noflatten=False, nordff=False, noshare=False, run=None, no_rw_check=False) → None

Run Yosys synthesis for the specified Verilog files.

deprecated: Use compile_design --synth-only instead.

collect_gl_sources(project, sim_lib_overrides) → list[Path]

Resolve every Verilog source the gate-level simulator needs.

Returns one self-contained source list so the caller can hand it to iverilog directly (no extra find in the Taskfile):

• the behavioural wrapper that keeps driving configuration (Fabric/*.v: eFPGA_top, the config controller, Frame_*, BlockRAM, models_pack …). The behavioural core eFPGA.v is excluded because the gate-level eFPGA.nl.v replaces it.

• the post-PnR fabric netlist (Fabric/macro/final_views holds exactly one *.nl.v, structural, instantiating tile macros by name),

• every tile netlist (Tile/<tile>/macro/final_views/nl/<tile>.nl.v),

• the PDK cell models the netlists bind against.

Parameters:

• project (Path) – Root of a FABulous project hardened through the GDS flow.

• sim_lib_overrides (list[str]) – Explicit PDK sim-cell library files or globs; skips auto-resolution.

Returns:

Behavioural wrapper, fabric netlist, tile netlists, then PDK cell models, in that order.

Raises:

• FileNotFoundError – If the fabric netlist or tile netlists are missing (the GDS flow has not been run).

• ValueError – If more than one fabric netlist is present.

resolve_sim_libs(project, overrides) → list[Path]

Resolve the PDK standard-cell Verilog sim models for project.

Honours overrides (files or globs) first; otherwise takes the active PDK and its install root from the FABulous context (which resolves FAB_PDK / FAB_PDK_ROOT and the ciel install) and globs <pdk_root>/<pdk>/libs.ref/<scl>/verilog/ for <scl>.v plus any *udp*.v / primitives.v companion (sky130 and gf180 ship their UDPs in a separate primitives.v; IHP inlines them).

Parameters:

• project (Path) – Root of a hardened FABulous project; used to anchor relative override globs.

• overrides (list[str]) – Explicit sim-cell library files or globs. When non-empty, PDK auto-resolution is skipped.

Returns:

Verilog cell-model files for the simulator.

Raises:

• FileNotFoundError – If an override matches nothing, or the resolved PDK sim file is missing.

• ValueError – If the context has no PDK or PDK root, or the PDK has no known default standard-cell library.