cmd_fabric_gen

Fabric and tile HDL-generation commands for the FABulous REPL.

Generate config memory, switch matrices, tiles, IO, and the fabric.

Classes

FabricGenCommandSet

Generate config memory, switch matrices, tiles, IO, and the fabric.

Module Contents

FabricGenCommandSet

class FabricGenCommandSet

Bases: ReplCommandSet

Generate config memory, switch matrices, tiles, IO, and the fabric.

Private reference to the CLI instance in which this CommandSet running.

This will be set when the CommandSet is registered and it should be accessed by child classes using the self._cmd property.

Methods

do_gen_all_tile(*_ignored) → None

Generate all tiles by calling do_gen_tile.

do_gen_bitStream_spec(*_ignored) → None

Generate bitstream specification of the fabric.

By calling genBitStreamSpec and saving the specification to a binary and CSV file.

Also logs the paths of the output files.

do_gen_config_mem(tiles) → None

Generate configuration memory of the given tile.

Parsing input arguments and calling genConfigMem.

Logs generation processes for each specified tile.

do_gen_fabric(*_ignored) → None

Generate fabric based on the loaded fabric.

Calling gen_all_tile and genFabric.

Logs start and completion of fabric generation process.

do_gen_geometry(padding=8) → None

Generate geometry of fabric for FABulator.

Checking if fabric is loaded, and calling ‘genGeometry’ and passing on padding value. Default padding is ‘8’.

Also logs geometry generation, the used padding value and any warning about faulty padding arguments, as well as errors if the fabric is not loaded or the padding is not within the valid range of 4 to 32.

do_gen_io_fabric(_args) → None

Generate I/O BELs for the entire fabric.

This command generates Input/Output Basic Elements of Logic (BELs) for all applicable tiles in the fabric, providing external connectivity across the entire FPGA design.

Parameters:

_args (str) – Command arguments (unused for this command).

do_gen_io_pin_config(tile, output=None) → None

Generate an IO pin configuration YAML file for a tile or supertile.

do_gen_io_tiles(tiles) → None

Generate I/O BELs for specified tiles.

This command generates Input/Output Basic Elements of Logic (BELs) for the specified tiles, enabling external connectivity for the FPGA fabric.

do_gen_model_npnr(*_ignored) → None

Generate Nextpnr model of fabric.

By parsing various required files for place and route such as pips.txt, bel.txt, bel.v2.txt and template.pcf. Output files are written to the directory specified by metaDataDir within projectDir.

Logs output file directories.

do_gen_switch_matrix(tiles) → None

Generate switch matrix of given tile.

Parsing input arguments and calling genSwitchMatrix.

Also logs generation process for each specified tile.

do_gen_tile(tiles) → None

Generate given tile with switch matrix and configuration memory.

Parsing input arguments, call functions such as genSwitchMatrix and genConfigMem. Handle both regular tiles and super tiles with sub-tiles.

Also logs generation process for each specified tile and sub-tile.

do_gen_top_wrapper(*_ignored) → None

Generate top wrapper of the fabric by calling genTopWrapper.

do_generate_custom_tile_config(tile_path, switch_matrix=True) → None

Generate a custom tile configuration for a given tile folder.

Or path to bel folder. A tile .csv file and a switch matrix .list file will be generated.

The provided path may contain bel files, which will be included in the generated tile .csv file as well as the generated switch matrix .list file.

do_run_FABulous_fabric(*_ignored) → None

Generate the fabric based on the CSV file.

deprecated: Use run_fab instead.

do_run_fab(*_ignored) → None

Generate the fabric based on the CSV file.

Create bitstream specification of the fabric, top wrapper of the fabric, Nextpnr model of the fabric and geometry information of the fabric.