ghdl¶

GHDL tool wrapper.

GHDL elaborates a VHDL design (--synth --out=verilog) and writes the resulting Verilog netlist to stdout. This wrapper captures that output so the VHDL-to-Verilog conversion no longer needs a raw subprocess call in the caller. Used as a singleton via GhdlTool.synthesize_to_verilog(...); never instantiated.

Classes¶

GhdlTool

Wraps the GHDL executable to elaborate VHDL into a Verilog netlist.

Module Contents¶

GhdlTool¶

class GhdlTool[source]¶

Bases: Tool

Wraps the GHDL executable to elaborate VHDL into a Verilog netlist.

Reject instantiation; tools are used only through their classmethods.

Parameters:

*_args (object) – Ignored positional arguments from the rejected constructor call.
**_kwargs (object) – Ignored keyword arguments from the rejected constructor call.

Raises:

TypeError – Always, because tool wrappers are stateless singletons.

Methods¶

classmethod executable() → Path | str[source]¶

Return the GHDL executable from the FABulous context.

Returns:: The configured GHDL executable.

classmethod synthesize_to_verilog(vhdl_file, models_pack, std='08') → str[source]¶

Elaborate a VHDL file into Verilog and return the Verilog text.

Parameters:

vhdl_file (Path) – The VHDL source file to elaborate. Its stem is used as the top-level entity name passed to -e.
models_pack (Path) – The FABulous models package GHDL needs on its analysis path.
std (str) – The VHDL standard passed to --std (default “08”).

Returns:

The Verilog netlist GHDL emits on stdout.