Using the eFPGA

This contains information on how to run and configure the RTL-to-bitstream flow for a FABulous fabric. The mainly consists of the steps place and route, synthesis and building he actual binary bitstream from a FASM file.

• Synthesis
  • Yosys models
  • Yosys compilation
    • Building
    • User guide
      • CLI Synthesis
      • Manual Synthesis
• Place and Route
  • Nextpnr models
  • Nextpnr compilation
    • Building
    • User guide
    • Primitive instantiation
    • Constraints for the placement of IO/bels
    • Footnotes
• FASM to Bitstream
  • User guide
    • Generate bitstream using CLI
    • Manually generate bitstream
    • Example
  • Changes in the primitives or adding new primitives