cmd_run_simulation

Run-simulation command implementation for the FABulous CLI.

RTL simulation exercises the behavioural fabric FABulous emits. Gate-level simulation (--gl) reuses the same testbench and bitstream but swaps the inner fabric core eFPGA and its tiles for the post-place-and-route netlists hardened by the GDS flow, linked against the PDK standard-cell models. The behavioural wrapper eFPGA_top (with its configuration controller) is kept, so the existing <design>_tb.v drives the mixed-level DUT unchanged.

Attributes

CMD_USER_DESIGN_FLOW
run_simulation_parser

Functions

collect_gl_sources(project, sim_lib_overrides)	Resolve every Verilog source the gate-level simulator needs.
do_run_simulation(self, args)	Simulate given FPGA design.
resolve_sim_libs(project, overrides)	Resolve the PDK standard-cell Verilog sim models for project.

Module Contents

CMD_USER_DESIGN_FLOW = 'User Design Flow'

collect_gl_sources(project, sim_lib_overrides) → list[Path]

Resolve every Verilog source the gate-level simulator needs.

Returns one self-contained source list so the caller can hand it to iverilog directly (no extra find in the Taskfile):

• the behavioural wrapper that keeps driving configuration (Fabric/*.v: eFPGA_top, the config controller, Frame_*, BlockRAM, models_pack …). The behavioural core eFPGA.v is excluded because the gate-level eFPGA.nl.v replaces it.

• the post-PnR fabric netlist (Fabric/macro/final_views holds exactly one *.nl.v, structural, instantiating tile macros by name),

• every tile netlist (Tile/<tile>/macro/final_views/nl/<tile>.nl.v),

• the PDK cell models the netlists bind against.

Parameters:

• project (Path) – Root of a FABulous project hardened through the GDS flow.

• sim_lib_overrides (list[str]) – Explicit PDK sim-cell library files or globs; skips auto-resolution.

Returns:

Behavioural wrapper, fabric netlist, tile netlists, then PDK cell models, in that order.

Raises:

• FileNotFoundError – If the fabric netlist or tile netlists are missing (the GDS flow has not been run).

• ValueError – If more than one fabric netlist is present.

do_run_simulation(self, args) → None

Simulate given FPGA design.

Uses Taskfile.yml (preferred) or falls back to Make (deprecated). The bitstream_file argument should be a binary file generated by ‘compile_design’. With --gl the hardened fabric netlist replaces the behavioural core for gate-level simulation.

resolve_sim_libs(project, overrides) → list[Path]

Resolve the PDK standard-cell Verilog sim models for project.

Honours overrides (files or globs) first; otherwise takes the active PDK and its install root from the FABulous context (which resolves FAB_PDK / FAB_PDK_ROOT and the ciel install) and globs <pdk_root>/<pdk>/libs.ref/<scl>/verilog/ for <scl>.v plus any *udp*.v / primitives.v companion (sky130 and gf180 ship their UDPs in a separate primitives.v; IHP inlines them).

Parameters:

• project (Path) – Root of a hardened FABulous project; used to anchor relative override globs.

• overrides (list[str]) – Explicit sim-cell library files or globs. When non-empty, PDK auto-resolution is skipped.

Returns:

Verilog cell-model files for the simulator.

Raises:

• FileNotFoundError – If an override matches nothing, or the resolved PDK sim file is missing.

• ValueError – If the context has no PDK or PDK root, or the PDK has no known default standard-cell library.

run_simulation_parser