# FABulous: An easy-to-use, silicon-proven (e)FPGA generator with an integrated CAD toolchain 🏗️ > FABulous: An easy-to-use, silicon-proven (e)FPGA generator with an integrated CAD toolchain 🏗️ v2.2.1.dev7+gad39353b9 2021, University of Manchester ## Pages - [FABulous: an Embedded FPGA Framework](index.html.md): FABulous is an open-source embedded FPGA (eFPGA) framework for generating FPGA fabric and integrates... - [Getting Started](getting_started/index.html.md): This section contains quick start setup and installation instructions to get FABulous running locall... - [Quick start](getting_started/quickstart.html.md): This guide walks you through installing FABulous, generating a fabric, and producing a bitstream in ... - [Using FABulous in GitHub Codespaces](getting_started/codespaces.html.md): GitHub Codespaces provides a complete, cloud-based development environment for FABulous with full GU... - [Installation Method](getting_started/installation/index.html.md): **Windows Support** - [`uv` based setup](getting_started/installation/uv.html.md): [uv](https://github.com/astral-sh/uv) is a high-performance Python package manager that provides fas... - [`venv` based setup](getting_started/installation/venv.html.md): Python >= 3.12 is required. The `venv` module is included with Python, but on some distributions you... - [Install Required CAD tools](getting_started/installation/cad-tool.html.md): We use [yosys](https://github.com/YosysHQ/yosys) for Verilog file parsing and [ghdl-yosys-plugin](ht... - [`docker` based setup](getting_started/installation/docker.html.md): We provide Docker images for FABulous that include all necessary tools and dependencies pre-installe... - [Nix-based Development Environment](getting_started/installation/nix-env.html.md): For the GDS backend flow, we use [Nix](https://nixos.org/) as our environment manager and developmen... - [User Guide](user_guide/index.html.md): This section provides all the information required to build your custom eFPGA and to use the fabrica... - [Building your eFPGA](user_guide/building_doc/index.html.md): This contains a guide and information on building your custom eFPGA. - [Fabric definition](user_guide/building_doc/fabric_definition.html.md): This section describes the process of modeling FABulous fabrics in a top-down manner. - [Fabric configuration](user_guide/building_doc/configuration.html.md): FABulous fabrics offer a 32-bit wide configuration port which can either be driven directly by e.g. ... - [Building fabric](user_guide/building_doc/building_fabric.html.md): The user can run the flow step by step as well (see below for instructions on building HDLs): - [FABulous Fabric Automation](user_guide/building_doc/fabric_automation.html.md): The fabric automation offers a set of tools and commands to automate common tasks - [Convert your design into GDSII format](user_guide/building_doc/fabric_gds.html.md): Once you have compiled your fabric RTL using the [building fabric](building_fabric.html.md) guide, y... - [Hardening through the LibreLane plugin](user_guide/building_doc/librelane_plugin.html.md): **This plugin is experimental.** - [WARNING](user_guide/building_doc/timing_characterization.html.md): The timing model produced by FABulous is experimental and has not been - [GDS Flow Configuration Variables](generated_doc/gds_variable.html.md): This is an auto-generated reference of all GDS flow configuration variables used by the FABulous GDS... - [CLI Usage Guide](user_guide/cli_doc/index.html.md): The FABulous command-line interface (CLI) provides a set of tools for generating eFPGA fabric projec... - [FABulous CLI — Features and Usage](user_guide/cli_doc/cli_feature.html.md): In FABulous, we provide two primary methods to drive the tool. First is the interactive REPL mode, w... - [Interactive CLI Commands Reference](generated_doc/interactive_cli_commands.html.md): This is an auto-generated reference of all FABulous CLI commands available in interactive mode. - [FABulous Configuration Variables](user_guide/cli_doc/fabulous_variable.html.md): FABulous can use environment variables to configure options, paths and projects. We distinguish betw... - [Using the eFPGA](user_guide/using_doc/index.html.md): This contains information on how to run and configure the RTL-to-bitstream flow for a FABulous fabri... - [Synthesis](user_guide/using_doc/synthesis/index.html.md): This contains information related to the synthesis step. - [Yosys models](user_guide/using_doc/synthesis/yosys.html.md): All Yosys model files can be found in the [Yosys repository](https://github.com/YosysHQ/yosys) under... - [Yosys compilation](user_guide/using_doc/synthesis/yosys_compilation.html.md): Yosys is used for logic synthesis and technology mapping of the Verilog Hardware Description Languag... - [Place and Route](user_guide/using_doc/pnr/index.html.md): This contains information related to the place and route step. - [Nextpnr models](user_guide/using_doc/pnr/nextpnr.html.md): After the FABulous flow has run successfully, the model files that describe your fabric - [Nextpnr compilation](user_guide/using_doc/pnr/nextpnr_compilation.html.md): Nextpnr can compile a JSON description of a circuit to FASM [1](#footnote-1) using the ar... - [Pin Constraints File (PCF)](user_guide/using_doc/pnr/pin_constraints.html.md): A pin constraints file (`.pcf`) maps the top-level ports of your user design to - [FASM to Bitstream](user_guide/using_doc/bitstream/bitstream_generation.html.md): This section contains information on how to generate a bitstream from a FASM file. - [Simulation and emulation](user_guide/simulation/index.html.md): This section describes how to verify and test a FABulous-generated fabric - [Simulation setup](user_guide/simulation/simulation.html.md): FABulous provides a simulation environment to validate that the generated - [Gate-level simulation](user_guide/simulation/gate_level_simulation.html.md): Gate-level (GL) simulation is the post-layout counterpart of - [Emulation setup](user_guide/simulation/emulation.html.md): This page describes *hardwired-bitstream* emulation. For running the fabric on a - [Emulating a fabric on a commercial FPGA](user_guide/simulation/emulation_on_fpga.html.md): This guide describes how to run a FABulous-generated fabric on a commercial FPGA - [Development](developer_guide/development.html.md): This page covers all aspects of contributing to FABulous, including development environment setup, c... - [Chip Gallery](gallery/index.html.md): eFPGA_RISCV_TSMC180: - [Team and Contact](misc/contact.html.md): FABulous is maintained by Professor Dirk Koch’s research groups at the [University of Manchester](ht... - [Publications](misc/publications.html.md): Page content - [API Reference](generated_doc/index.html.md): This section contains the complete software documentation for FABulous. - [fabulous](generated_doc/fabulous/index.html.md): FABulous FPGA framework package. - [custom_exception](generated_doc/fabulous/custom_exception/index.html.md): Custom exception classes for the FABulous framework. - [fabric_cad](generated_doc/fabulous/fabric_cad/index.html.md): Computer-aided design (CAD) tools for FPGA fabric development. - [gen_bitstream_spec](generated_doc/fabulous/fabric_cad/gen_bitstream_spec/index.html.md): Bitstream specification generation module. - [gen_design_top_wrapper](generated_doc/fabulous/fabric_cad/gen_design_top_wrapper/index.html.md): User design top wrapper generation module. - [gen_npnr_model](generated_doc/fabulous/fabric_cad/gen_npnr_model/index.html.md): Nextpnr model generation for FABulous FPGA fabrics. - [timing_model](generated_doc/fabulous/fabric_cad/timing_model/index.html.md): Timing model package for FABulous. - [FABulous_timing_model](generated_doc/fabulous/fabric_cad/timing_model/FABulous_timing_model/index.html.md): Defines the FABulousTileTimingModel class. - [FABulous_timing_model_interface](generated_doc/fabulous/fabric_cad/timing_model/FABulous_timing_model_interface/index.html.md): Define the FABulousTimingModelInterface class. - [hdlnx](generated_doc/fabulous/fabric_cad/timing_model/hdlnx/index.html.md): Package for graph operations on HDLnx timing graphs. - [hdlnx_timing_model](generated_doc/fabulous/fabric_cad/timing_model/hdlnx/hdlnx_timing_model/index.html.md): Convertes verilog RTL into a verilog gate-level netlist. - [sdfnx](generated_doc/fabulous/fabric_cad/timing_model/hdlnx/sdfnx/index.html.md): Package for SDF to Timing Graph Conversion. - [sdf_to_graph](generated_doc/fabulous/fabric_cad/timing_model/hdlnx/sdfnx/sdf_to_graph/index.html.md): SDF to Timing Graph Conversion Module. - [sdf_to_graph_base](generated_doc/fabulous/fabric_cad/timing_model/hdlnx/sdfnx/sdf_to_graph_base/index.html.md): SDF Timing Graph Class Module. - [timing_graph](generated_doc/fabulous/fabric_cad/timing_model/hdlnx/sdfnx/timing_graph/index.html.md): SDF Timing Graph Generation Module. - [verilog_gate_level](generated_doc/fabulous/fabric_cad/timing_model/hdlnx/verilog_gate_level/index.html.md): Convert a Verilog gate-level netlist into a timing graph. - [models](generated_doc/fabulous/fabric_cad/timing_model/models/index.html.md): Models for the SDF timing model generation and analysis. - [tools](generated_doc/fabulous/fabric_cad/timing_model/tools/index.html.md): Package for various cad toos. - [specification](generated_doc/fabulous/fabric_cad/timing_model/tools/specification/index.html.md): Define the abstract base classes for synthesis STA tool backends. - [sta_tools](generated_doc/fabulous/fabric_cad/timing_model/tools/sta_tools/index.html.md): Static Timing Analysis Tools Package. - [opensta](generated_doc/fabulous/fabric_cad/timing_model/tools/sta_tools/opensta/index.html.md): OpenSTA Tool Interface. - [synth_tools](generated_doc/fabulous/fabric_cad/timing_model/tools/synth_tools/index.html.md): Synthesis Tools Package. - [yosys](generated_doc/fabulous/fabric_cad/timing_model/tools/synth_tools/yosys/index.html.md): Yosys Tool Interface, which uses Yosys to synthesize a Verilog design. - [fabric_definition](generated_doc/fabulous/fabric_definition/index.html.md): FABulous fabric definition module. - [bel](generated_doc/fabulous/fabric_definition/bel/index.html.md): Basic Element of Logic (BEL) definition module. - [cell_spec](generated_doc/fabulous/fabric_definition/cell_spec/index.html.md): Standard-cell specifications for timing characterization. - [configmem](generated_doc/fabulous/fabric_definition/configmem/index.html.md): Configuration memory definition module. - [define](generated_doc/fabulous/fabric_definition/define/index.html.md): Fabric definition enumerations and constants. - [fabric](generated_doc/fabulous/fabric_definition/fabric/index.html.md): FPGA fabric definition module. - [gen_io](generated_doc/fabulous/fabric_definition/gen_io/index.html.md): Generated I/O definition module. - [port](generated_doc/fabulous/fabric_definition/port/index.html.md): Port class hierarchy for FPGA fabric. - [supertile](generated_doc/fabulous/fabric_definition/supertile/index.html.md): Supertile definition for FPGA fabric. - [switch_matrix](generated_doc/fabulous/fabric_definition/switch_matrix/index.html.md): Switch matrix construct for the FABulous fabric model. - [tile](generated_doc/fabulous/fabric_definition/tile/index.html.md): Tile class definition for FPGA fabric representation. - [wire](generated_doc/fabulous/fabric_definition/wire/index.html.md): Wire class for managing connections between tiles. - [yosys_obj](generated_doc/fabulous/fabric_definition/yosys_obj/index.html.md): Object representation of the Yosys Json file. - [fabric_generator](generated_doc/fabulous/fabric_generator/index.html.md): FABulous fabric generator module. - [code_generator](generated_doc/fabulous/fabric_generator/code_generator/index.html.md): Code generator module for FABulous. - [code_generator](generated_doc/fabulous/fabric_generator/code_generator/code_generator/index.html.md): The base class for all code generators. - [code_generator_VHDL](generated_doc/fabulous/fabric_generator/code_generator/code_generator_VHDL/index.html.md): The VHDL code generator. - [code_generator_Verilog](generated_doc/fabulous/fabric_generator/code_generator/code_generator_Verilog/index.html.md): The Verilog code generator. - [gds_generator](generated_doc/fabulous/fabric_generator/gds_generator/index.html.md): GDS generation for FABulous. - [flows](generated_doc/fabulous/fabric_generator/gds_generator/flows/index.html.md): FABulous GDS Generator - LibreLane Custom Flows. - [fabric_macro_flow](generated_doc/fabulous/fabric_generator/gds_generator/flows/fabric_macro_flow/index.html.md): Stitching flow to assemble FABulous tile macros into a complete fabric. - [fabric_optimisation_flow](generated_doc/fabulous/fabric_generator/gds_generator/flows/fabric_optimisation_flow/index.html.md): Full automatic fabric flow with LP-based tile optimisation. - [flow_define](generated_doc/fabulous/fabric_generator/gds_generator/flows/flow_define/index.html.md): Defines the standard flow for generating GDS from RTL. - [plugin_fabric_flow](generated_doc/fabulous/fabric_generator/gds_generator/flows/plugin_fabric_flow/index.html.md): Config-driven LibreLane plugin adapter for the FABulous fabric flow. - [plugin_tile_flow](generated_doc/fabulous/fabric_generator/gds_generator/flows/plugin_tile_flow/index.html.md): Config-driven LibreLane plugin adapter for the FABulous tile flow. - [tile_macro_flow](generated_doc/fabulous/fabric_generator/gds_generator/flows/tile_macro_flow/index.html.md): Tile optimisation flows for FABulous fabric generation. - [gen_io_pin_config_yaml](generated_doc/fabulous/fabric_generator/gds_generator/gen_io_pin_config_yaml/index.html.md): Generate IO pin order configuration files for FABulous tiles and fabrics. - [helper](generated_doc/fabulous/fabric_generator/gds_generator/helper/index.html.md): Helper utilities for GDS generation: die area, pitch, step substitution. - [script](generated_doc/fabulous/fabric_generator/gds_generator/script/index.html.md): Script used by steps during GDS generation. - [fabric_io_place](generated_doc/fabulous/fabric_generator/gds_generator/script/fabric_io_place/index.html.md): Place fabric-level signal BPins, halo-aware. - [odb_power](generated_doc/fabulous/fabric_generator/gds_generator/script/odb_power/index.html.md): OpenDB script to connect power rails for FABulous fabric. - [odb_protocol](generated_doc/fabulous/fabric_generator/gds_generator/script/odb_protocol/index.html.md): Protocols for ODB objects used in FABulous. - [tile_io_place](generated_doc/fabulous/fabric_generator/gds_generator/script/tile_io_place/index.html.md): Utilities for placing IO pins by expanding configuration segments. - [vhdl_json_header](generated_doc/fabulous/fabric_generator/gds_generator/script/vhdl_json_header/index.html.md): Generate a JSON header for a VHDL design using the GHDL Yosys plugin. - [steps](generated_doc/fabulous/fabric_generator/gds_generator/steps/index.html.md): FABulous GDS Generator - LibreLane Custom Steps. - [add_buffer](generated_doc/fabulous/fabric_generator/gds_generator/steps/add_buffer/index.html.md): FABulous GDS Generator - Add Buffers Step. - [auto_diode](generated_doc/fabulous/fabric_generator/gds_generator/steps/auto_diode/index.html.md): Auto-diode insertion step for FABulous fabric generator. - [condition_magic_drc](generated_doc/fabulous/fabric_generator/gds_generator/steps/condition_magic_drc/index.html.md): FABulous GDS Generator - Conditional Magic DRC Step. - [diodes_on_ports](generated_doc/fabulous/fabric_generator/gds_generator/steps/diodes_on_ports/index.html.md): FABulous GDS Generator - Diodes on Ports step. - [extract_pdk_info](generated_doc/fabulous/fabric_generator/gds_generator/steps/extract_pdk_info/index.html.md): Extract PDK placement site dimensions step. - [fabric_IO_placement](generated_doc/fabulous/fabric_generator/gds_generator/steps/fabric_IO_placement/index.html.md): FABulous GDS Generator - FABulous I/O Placement Step. - [fabric_area_opt](generated_doc/fabulous/fabric_generator/gds_generator/steps/fabric_area_opt/index.html.md): FABulous GDS Generator - NLP optimisation Step using pymoo. - [magic_streamout](generated_doc/fabulous/fabric_generator/gds_generator/steps/magic_streamout/index.html.md): FABulous Magic StreamOut - syncs DIE_AREA env with state’s design_\_die_\_bbox. - [odb_connect_pdn](generated_doc/fabulous/fabric_generator/gds_generator/steps/odb_connect_pdn/index.html.md): FABulous GDS Generator - ODB Power Connection Step. - [round_die_area](generated_doc/fabulous/fabric_generator/gds_generator/steps/round_die_area/index.html.md): FABulous GDS Generator - Round Die Area Step. - [tile_IO_placement](generated_doc/fabulous/fabric_generator/gds_generator/steps/tile_IO_placement/index.html.md): Custom IO placement step for FABulous tiles. - [tile_area_opt](generated_doc/fabulous/fabric_generator/gds_generator/steps/tile_area_opt/index.html.md): Tile size optimisation step for FABulous fabric generator. - [timed_detailed_routing](generated_doc/fabulous/fabric_generator/gds_generator/steps/timed_detailed_routing/index.html.md): Detailed Routing step with a hard wall-clock timeout. - [vhdl_json_header](generated_doc/fabulous/fabric_generator/gds_generator/steps/vhdl_json_header/index.html.md): Custom JSON-header step that reads VHDL through the GHDL Yosys plugin. - [while_step](generated_doc/fabulous/fabric_generator/gds_generator/steps/while_step/index.html.md): A template for while loop steps. - [gen_fabric](generated_doc/fabulous/fabric_generator/gen_fabric/index.html.md): Fabric generation utilities module. - [fabric_automation](generated_doc/fabulous/fabric_generator/gen_fabric/fabric_automation/index.html.md): Functions for fabric automation, such as generating tile configurations and IOs. - [gen_configmem](generated_doc/fabulous/fabric_generator/gen_fabric/gen_configmem/index.html.md): Configuration memory generation module. - [gen_fabric](generated_doc/fabulous/fabric_generator/gen_fabric/gen_fabric/index.html.md): Fabric generation module for FABulous FPGA architecture. - [gen_switchmatrix](generated_doc/fabulous/fabric_generator/gen_fabric/gen_switchmatrix/index.html.md): Switch matrix generation module for FABulous FPGA tiles. - [gen_tile](generated_doc/fabulous/fabric_generator/gen_fabric/gen_tile/index.html.md): Tile generation module for FABulous FPGA architecture. - [gen_top_wrapper](generated_doc/fabulous/fabric_generator/gen_fabric/gen_top_wrapper/index.html.md): Top-level wrapper generation module. - [parser](generated_doc/fabulous/fabric_generator/parser/index.html.md): Parser module for FABulous. - [parse_configmem](generated_doc/fabulous/fabric_generator/parser/parse_configmem/index.html.md): Configuration memory parser for FABulous FPGA tiles. - [parse_csv](generated_doc/fabulous/fabric_generator/parser/parse_csv/index.html.md): Contains functions for parsing CSV files related to the fabric definition. - [parse_hdl](generated_doc/fabulous/fabric_generator/parser/parse_hdl/index.html.md): Contains functions for processing BEL related information from HDL files. - [parse_switchmatrix](generated_doc/fabulous/fabric_generator/parser/parse_switchmatrix/index.html.md): Parser functions for switch matrix and list file configurations. - [fabulous](generated_doc/fabulous/fabulous/index.html.md): FABulous command-line interface entry point. - [fabulous_api](generated_doc/fabulous/fabulous_api/index.html.md): FABulous API module for fabric and geometry generation. - [fabulous_repl](generated_doc/fabulous/fabulous_repl/index.html.md): REPL module for FABulous. - [cmd_fabric_gen](generated_doc/fabulous/fabulous_repl/cmd_fabric_gen/index.html.md): Fabric and tile HDL-generation commands for the FABulous REPL. - [cmd_gui](generated_doc/fabulous/fabulous_repl/cmd_gui/index.html.md): GUI-launcher commands for the FABulous REPL. - [cmd_helper](generated_doc/fabulous/fabulous_repl/cmd_helper/index.html.md): Helper inspection commands for the FABulous REPL. - [cmd_macro](generated_doc/fabulous/fabulous_repl/cmd_macro/index.html.md): GDS macro-hardening flow commands for the FABulous REPL. - [cmd_script](generated_doc/fabulous/fabulous_repl/cmd_script/index.html.md): Script-execution commands for the FABulous REPL. - [cmd_setup](generated_doc/fabulous/fabulous_repl/cmd_setup/index.html.md): Setup and project-management commands for the FABulous REPL. - [cmd_timing](generated_doc/fabulous/fabulous_repl/cmd_timing/index.html.md): Timing-model characterization command for the FABulous REPL. - [cmd_user_design](generated_doc/fabulous/fabulous_repl/cmd_user_design/index.html.md): User-design flow commands for the FABulous REPL. - [command_set_base](generated_doc/fabulous/fabulous_repl/command_set_base/index.html.md): Shared infrastructure for FABulous REPL command groups. - [fabulous_repl](generated_doc/fabulous/fabulous_repl/fabulous_repl/index.html.md): FABulous interactive shell. - [helper](generated_doc/fabulous/fabulous_repl/helper/index.html.md): Helper functions and utilities for the FABulous REPL. - [fabulous_settings](generated_doc/fabulous/fabulous_settings/index.html.md): FABulous settings management and environment configuration. - [geometry_generator](generated_doc/fabulous/geometry_generator/index.html.md): FABulous geometry generator module. - [bel_geometry](generated_doc/fabulous/geometry_generator/bel_geometry/index.html.md): Class for generating and managing the geometry of BELs. - [fabric_geometry](generated_doc/fabulous/geometry_generator/fabric_geometry/index.html.md): Classes for generating and managing the geometry of FPGA fabrics. - [geometry_gen](generated_doc/fabulous/geometry_generator/geometry_gen/index.html.md): Classes for geometry generation. - [geometry_obj](generated_doc/fabulous/geometry_generator/geometry_obj/index.html.md): Simple FPGA geometry location base object class. - [port_geometry](generated_doc/fabulous/geometry_generator/port_geometry/index.html.md): Port geometry definitions. - [sm_geometry](generated_doc/fabulous/geometry_generator/sm_geometry/index.html.md): Switch matrix geometry definitions. - [tile_geometry](generated_doc/fabulous/geometry_generator/tile_geometry/index.html.md): Tile geometry generation and management for FABulous FPGA tiles. - [wire_geometry](generated_doc/fabulous/geometry_generator/wire_geometry/index.html.md): Wire geometry classes for FABulous FPGA routing structures. - [processpool](generated_doc/fabulous/processpool/index.html.md): A custom ProcessPoolExecutor that uses dill for serialization. - [tools](generated_doc/fabulous/tools/index.html.md): Package for various cad toos. - [ghdl](generated_doc/fabulous/tools/ghdl/index.html.md): GHDL tool wrapper. - [opensta](generated_doc/fabulous/tools/opensta/index.html.md): OpenSTA tool wrapper: static timing analysis of a gate-level netlist. - [tool](generated_doc/fabulous/tools/tool/index.html.md): Abstract base for external EDA tool wrappers. - [yosys](generated_doc/fabulous/tools/yosys/index.html.md): Yosys tool wrapper: converts Verilog into Yosys’s JSON netlist format. --- For more comprehensive documentation, see [llms-full.txt](llms-full.txt)