supertile

Supertile definition for FPGA fabric.

This module contains the SuperTile class, which represents a composite tile made up of multiple smaller, individual tiles. Supertiles allow for the creation of more larger, complex and hierarchical structures within the FPGA fabric, combining different functionalities into a single, reusable block.

Classes

SuperTile

Store the information about a super tile.

Module Contents

SuperTile

class SuperTile[source]

Store the information about a super tile.

Variables:

  • name (str) – The name of the super tile.

  • tileDir (Path) – Path to the tile directory.

  • tiles (list[Tile]) – The list of tiles that make up the super tile.

  • tileMap (list[list[Tile]]) – The map of the tiles that make up the super tile

  • bels (list[Bel]) – The list of bels of that the super tile contains

  • withUserCLK (bool) – Whether the super tile has a userCLK port. Default is False.

  • supertile_matrix_dir (Path | None) – Path to the supertile switch matrix file (.list or .csv), or None if no supertile switch matrix exists.

  • supertile_matrix_config_bits (int) – Number of configuration bits required by the supertile switch matrix.

  • master_tile_coords (tuple[int, int] | None) – Local (x, y) of the master tile. Explicitly set via the MASTER token in the supertile CSV, or computed as the last non-None tile in row-major order if no MASTER is present. All supertile config bits and BELs are anchored to this tile.

Properties

property max_height: int[source]

Return the maximum height of the supertile.

property max_width: int[source]

Return the maximum width of the supertile.

property total_config_bits: int[source]

switch matrix bits plus BEL bits.

Type:

Return the supertile’s config bits

Methods

getInternalConnections() → list[tuple[list[Port], int, int]][source]

Return all the internal connections of the supertile.

Returns:

A list of tuples which contains the internal connected port and the x and y coordinate of the tile.

getPortsAroundTile() → dict[str, list[list[Port]]][source]

Return all the ports that are around the supertile.

The dictionary key is the location of where the tile is located in the supertile map with the format of “X{x}Y{y}”, where x is the x coordinate of the tile and y is the y coordinate of the tile. The top left tile will have key “00”.

Returns:

The dictionary of the ports around the super tile.

get_all_input_sjump_ports() → list[tuple[int, int, Port]][source]

Return all SJUMP INPUT ports across every child tile.

Returns:

Each entry is (local_x, local_y, port) for every INPUT port with wireDirection == Direction.SJUMP in any child tile.

get_all_sjump_ports() → list[tuple[int, int, Port]][source]

Return all SJUMP OUTPUT ports across every child tile.

Returns:

Each entry is (local_x, local_y, port) for every OUTPUT port with wireDirection == Direction.SJUMP in any child tile.

get_master_tile_coords() → tuple[int, int][source]

Return the (x, y) coordinates of the master tile in local space.

The master tile is either:

  • The tile explicitly marked with MASTER in the supertile CSV (stored in master_tile_coords), or

  • The last non-None tile in row-major order if no MASTER was specified.

Config bits for the supertile switch matrix and BELs are chained through this tile’s frame path, and the BEL placement (nextpnr model, bitstream spec) is anchored here. This is distinct from the supertile’s structural anchor tile (the top-left tile, where gen_fabric places the wrapper instance); the master and the anchor are usually different tiles (e.g. DSP master = DSP_bot, anchor = DSP_top).

Returns:

(x, y) in local supertile coordinates.

Raises:

ValueError – If the supertile contains no tiles.

get_matrix_port_names() → tuple[set[str], set[str]][source]

Return the valid source and sink names for the supertile switch matrix.

The names mirror what gen_super_tile_switch_matrix declares as matrix ports, so they form the authoritative set against which a supertile_matrix file is validated. Constant sources (GND0 etc.) are not included here; callers add them separately.

Returns:

(valid_sources, valid_sinks) where sources drive the matrix muxes (child OUTPUT SJUMP wires and BEL outputs) and sinks are the mux outputs (BEL inputs and child INPUT SJUMP wires).

get_min_die_area(x_pitch, y_pitch, x_pin_thickness_mult=Decimal(1), y_pin_thickness_mult=Decimal(1), edge_offset=2) → tuple[Decimal, Decimal][source]

Calculate minimum SuperTile dimensions based on IO pin track requirements.

Takes the maximum per-side IO pin count across all constituent subtiles as a conservative upper bound, then derives the minimum physical width and height required.

See Tile.get_min_die_area for the track-based derivation.

Parameters:

  • x_pitch (Decimal) – Vertical-layer track pitch (for north/south pins).

  • y_pitch (Decimal) – Horizontal-layer track pitch (for east/west pins).

  • x_pin_thickness_mult (Decimal) – Number of tracks each north/south pin spans, by default 1.

  • y_pin_thickness_mult (Decimal) – Number of tracks each east/west pin spans, by default 1.

  • edge_offset (int, optional) – Reserved tracks at tile edge, by default 2.

Returns:

(min_width, min_height)